INTRODUCTION In this paper, we present IVA-HD, a true multistandard, programmable, full HD video coding engine which adopts optimal hardware The TI DM3730 application processor addresses these challenges with a dedicated video coding engine built with algorithm-specific hardware accelerators. The 2 macro block pipeline cannot support this requirement without impacting the performance or the bit rate. Video conferencing not only requires low latency but also requires encoding with a fixed limit on the number of bits per slice. The approach of decoupling stream processing and pixel processing, and using a 2 macroblock pipeline helps meet the performance, but introduces a frame delay resulting in higher latency. Multicore programmable processors can support multiple standards, but are not scalable to meet full HD performance of complex standards like H.264 High Profile (HP) in a low-power CMOS process, and are inefficient in terms of area and power. Low power is typically achieved by using single codec optimized circuitry and massive parallelism so that the design can run at lower voltage and frequency. Low power video codecs employ hardwired implementations targeted to a specific standard and address either encode or decode. Low power and area efficiency are also equally critical requirements for these applications. There is increasing demand for higher visual quality, and the wide spectrum of video content requires support for multiple standards. The functionality ranges from single channel encoding (camcorder) and decoding (video playback), to more complex use cases such as video conferencing (encode + decode) and transcoding. Full HD video coding has become an essential requirement.
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March 2023
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